Nowadays, the wireless communication industry plays a much important role in the economic advancement. A variety of Radio Frequency (RF) circuit designs and researches are provided for improving the efficiency or performance of the RF devices.
With respect to the radio frequency transceiver circuit or sub-circuit, such as a low noise amplifier or a power amplifier, the input/output (I/O) pad is exposed directly to the environment through an antenna or other I/O element. Thus, it is possible for the RF transceiver circuit or sub-circuit to be damaged by the electrostatic discharge (ESD) that occurs in the environment because of the weather or other artificial interference.
A traditional ESD protection circuit is shown in FIG. 1. The ESD protection circuit 16 is attached to the I/O pad 14 of the RF circuit 12. The ESD protection circuit 16 comprises a diode 161 connected between the I/O pad 14 and the power source VC, and a diode 163 connected between the I/O pad 14 and the ground. Wherein the diode 161 is used as a positive ESD path, and the diode 163 is used as a negative ESD path.
When a positive ESD occurs at the I/O pad 14, the diode 161 will be under forward-biased condition, and the ESD current will be conducted to the power source VC through the positive ESD path. When a negative ESD occurs at the I/O pad 14, the diode 163 will be under forward-biased condition, and the ESD current will be conducted to the ground through the negative ESD path.
For an ESD protection circuit, the more ESD paths are comprised, the less discharging time is needed, and the more robust the ESD protection circuit is. On the other hand, if there are more diodes used as ESD paths in the ESD protection circuit, the larger the parasitic capacitance is, and the performance of the RF circuit will be degraded much seriously.
Referring to FIG. 2, there is shown a schematic diagram of another conventional ESD protection circuit. The ESD protection circuit 20 is attached to the I/O pad 203 of the RF circuit 201. The ESD protection circuit 20 comprises a plurality of diodes 221, 223, 225, 241, 243, and 245. The diodes 221, 223, and 225 are connected between the power source 205 and the I/O pad 203 in series forming a positive ESD path. The diodes 241, 243, and 245 are connected between the I/O pad 203 and the ground 207 in series forming a negative ESD path.
The ESD path with a plurality of diodes connected in series can abide much higher voltage ESD stress. And the series connecting structure reduces the total parasitic capacitance of diodes.
However, each ESD path of the ESD protection circuit 20 comprises three diodes. In other words, the turn-on voltage of the ESD path is higher than three times of the threshold voltage of the diode. If the ESD voltage is lower than three times of the threshold voltage of the diode, the ESD path will not be turned-on, and the RF circuit 201 may be damaged by the ESD current.
Furthermore, as the number of diodes connected in series increases, the parasitic capacitance 32 reduces, and the equivalent impedance 34 of the ESD path increases linearly, as shown in FIG. 3. If the equivalent impedance of the ESD path increases, the ESD current conducting will be less efficient.